I’m working on a 2-transistor flyback DC-DC with EPC2088 switches. The controller is the standard UC1845 family, 50% max duty cycle, peak current mode control. The current sense resistor is normally placed in series with the source of the lower switch. Since this part has a 1 V current sense peak limit, AND I don’t want to lose up to 1 V of gate drive (as well as adding the extra parasitic inductance), how is this normally handled?
Choose a controller with a lower 0.1 V peak current limit. Find a low inductance packaged sense resistor and layout very carefully in series with the source. Not crazy about this.
Put the current sense resistor in the drain and use a high CMRR current sense amplifier like the INA241 (but not suitable for high frequency Fsw) or more likely the INA296 to measure the current and amplify the signal for lower resistor dissipation.
A current transformer- no space for it in this design.
Hi, thanks for writing in! Besides the 1 V, another issue is the gate drive moving up and down as Source moves up and down. Another way this is commonly handled is to use an add-on gate driver that is designed to accommodate a current sense resistor in the Source leg. One example is ONSemi’s NCP51820, a made-for-GaN half-bridge gate driver (but you could just use the bottom one) that allows 2 grounds: input signal ground, and power Source gate return (+/- 3.5 V difference from power ground). Another example is an isolated gate driver, such as Skyworks Si827x series or ADI isolated drivers, with an output 5V that is referenced to the Source pin (not referenced to the power ground).