Drain-source thermal resistance

Designing with GaN FETs and ICs
1

There’s plenty of resources and design guides and specs on thermal resistance between junction and case and ambient etc. and thermal design regarding heatsinking, but what about the thermal resistance between drain and source?

I have an application where I’m switching a load (50% duty cycle, ~1MHz) that will get hot and needs to be managed. Right now I’m using a high side switch so the load’s negative terminal can be connected directly to a large copper pour + vias to a heatsunk ground for thermal management. I’d like to switch with a low-side GaN switch for higher efficiency and no bootstrapping, but I’m afraid that the load will no longer have a good thermal path to heatsunk ground.

Is there any available data on heat transfer from drain to source when switch is ON vs OFF?

2

Hi, thanks for your question. The construction of EPC’s GaN FETs are different from MOSFETs… they are lateral, which means that both Drain and Source (and Gate) are all on the side of the FET that faces down to the board. The heat has a good thermal path from either the Drain and/or the Source pins to the PCB. And yes, copper pours can help, and don’t need to be equally spread between Drain and Source pins.
Here is a link to an example thermal model, it is a PDF file. This example is for the 100 V FET EPC2204: https://epc-co.com/epc/portals/0/epc/documents/models/thermal/EPC2204%20Thermal%20SPICE%20Model%20for%20web.pdf
The small cells inside the FET help the heat move very well between the many Source and Drain connections, and to the external pins.
I hope this helps.