Dear EPC forum,
I am currently finishing a PCB layout of a 500W SMPS. The last remaining design rule warning is caused by the EPC2304, stating: “Padstack is questionable (negative solder mask clearance is larger than pad; no solder mask will be generated)”.
In all honesty I do not have any idea what this implies, or if it is even a true error. If you know, please let me know what is going on, and how I might solve this issue. Thank you.