I am working with a 3-phase PMAC motor drives using EPC2304 and EPC2305 without antiparallel Schottky diodes.
I have far more experience with IGBT and MOSFET inverters, and generally the GaN inverter runs as I would expect, except when disabling the bridge (simultaneously turning off all 6 switches) while the motor is driven with some amount of current. When the inverter is disabled and high currents are flowing, we see the DC Bus link increase in voltage for a brief period (100uS to 1mS). The duration and magnitude of this increased voltage depends on bus capacitance and the amount of motor current flowing when the inverter is disabled (and perhaps motor winding impedance).
Running the same test on an IGBT inverter does not show this behavior. I suspect it is due to the reverse-conduction resistance of the GaN FET while currents are circulating and dissipating in the bridge right after inverter disable, but I would think the voltage should clamp to approximately the reverse Vds value. I am seeing the bus increase by 50% over the nominal DC bus in some instances (Reaching 80+V on a 40V bus).
Is there another possible cause for this behavior? I have seen a number of reference designs that do not use external Schottky diodes, but I have not seen this topic addressed anywhere so far.
Hi Allen,
The di/dt is a lot faster with GaN. In my last projected, I saw a 3 ns turn off time. A newer faster generation 40 A IGBT at 90 C is more than 10 times slower at turn off. If you consider high currents and PCB inductance, you’re going to get a lot of V from V=Ldi/dt. You may need more capacitance to absorb that energy or improve your PCB layout to reduce your inductance. The best way to achieve a “best design” is to start your PCB layout with high frequency GaN in mind. The common mistake is to keep 99% of the PCB layout the same as it was for the IGBT layout, and simply change the footprint to drop in GaN device.
Regards,
Perry Rothenbaum
Perry, I appreciate the response. Is this a phenomenon you have seen in your high-current reference designs? We have an entirely new PCB layout which we belielved minimized inductance (with the tradeoffs that come with using a single-layer PCB to accommodate an aluminum-substrate PCB design though).
What factor does the motor inductance play into this? It would seem that the energy stored in the motor windings at the instant that the inverter is disabled would have to go somewhere, presumably into the DC Bus and circulating through the reverse-conducting GaN FETs. Do the GaN FETs exhibit a large voltage drop considering the reverse-bias Vgd threshold voltage + current * Rds(on)? And does Rds(on) increase significantly in the reverse-conducting direction as compared to the forward-conducting direction?
Hello Allen,
what is the amount of overshoot? Could you please share waveforms? Also, do you have long cabling between the power supply and the inverter? Can you share a block diagram of your setup?
We can also take this offline and do a design review of your board. Where is your company based?
Best regards
Thanks for reaching out, and it is probably a good idea to take this offline. We are based in Virginia, United States. You should have my email address, so feel free to reach out to me there.