How does EPC handle the “Miller Effect”?
“Miller Capacitance”, CGD, is quite low for these devices. Therefore, switching losses due to the “Miller Effect” are quite low. Handling the “Miller Effect” during a dv/dt is similar to handling it in MOSFETs. In low voltage devices, the capacitive divider between CGD and CGS is enough to keep the device off. At higher voltages, a low impedance turn off path is required to keep a device off under high dv/dt. EPC makes it easy to drive our eGaN FETs by working with IC companies to produce driver ICs that effectively manage the turn on and turn off of eGaN FETs at very high dv/dt.