Reduce negative reverse voltage at the transistor

Hello, what are the different effective techniques to reduce the negative peak discharge pulse generated at the EPC GaN FET? it’s quite narrow and sometimes could achieve the level of the discharge pulse. A measurement image is attached.

image

Hello,
the waveform depends on details of your circuit and working voltages.
Some missing waveform of capacitor voltage and FET drain voltage will also help to understand. It is better if we can take the discussion offline since you’ll need to share details of your implementation.

  1. The waveform is typical of a resonant discharge pulser, with the pulse prematurely interrupted by opening (turning off) the FET
  2. The waveform shape looks pointing to a resonant frequency of about 8 MHz, which is consistent with about 2nH and about 200nF capacitance
  3. The bus voltage looks to be in the order of 20V, but we need a waveform here (of the capacitor voltage and possibly of the FET drain voltage).
  4. The measured current in the shunt is actually the capacitor current, which is equal to the recharge current (in RCHRG) minus the discharge current. Your waveform is plotted inverted. When you turn off the FET, there is a transient which is a current step. The current in the RCHRG and related parasitic inductance will be pushed in the capacitors. Also, the zero in the shunt due to parasitic inductance can increase the measured step and create an undershoot and needs to be compensated properly.

Regards