The high frequency capability of the devices could be an issue with the layout of my circuit board. What must I be mindful of when laying out my circuit?
Generally, the eGaN FET should be treated as any other MOSFET, keeping in mind that it does have the capability of higher performance operation because of its relatively low total gate charge (Qg) and small CRSS. Some general guidelines:
- Drive the gate with 5 V, keep max gate voltage below 5.5 V. There are several ICs available to make this task easy.
- Minimize gate source circuit impedance. It is advisable keep the gate source loop as small as possible, even at the cost of longer paths in drain circuit.
- Use a low impedance driver
- There are driver IC’s developed to optimize the performance of eGaN FETs in circuit. For a list of current available eGaN FET optimized IC’s please see the eGaN Drivers and Controllers page.
The “Using Enhancement Mode GaN-on-Silicon Power FETs application note, has further information. In addition, land pad layouts that minimize inductance can be found on all EPC data sheets on the Product Selector Guide for eGaN FETs and ICs page. Chapter 3 of the book titled, “GaN Transistors for Efficient Power Conversion” covers this topic in detail. Layout techniques to minimize switching time and voltage overshoot can be found in the white paper Impact of Parasitics on Performance and the white paper Optimizing PCB Layout. There is also a video that you can review at “How To GaN 05: Design Basics – Layout”.