TI's LM5177 with EPC2071 design support

Hi Sir,

We plan use TI’s LM5177 with EPC2071 design for 36-48VDC converter to 48VDC. May I know EPC have any suggestion or reference design for gate circuit to suppress the crosstalk and di/dt effect?

we are actually developing a board with the LM5177 called EPC9178, it should be available in a month or so.
The main recommendation I have is to pay attention to the layout to minimize parasitic inductances (common source inductance, power loop inductance, and gate loop inductance). This is mainly done by:
1- using vertical layout utilizing the top and first inner layer on the PCB
2- putting the power and gate drive loops at exactly 90° to each other
3- implementing a kelvin point on the PCB connecting the power and gate drive loops
I suggest you take a look at:

Dear Sir,

Thank you very much! look forward EPC9178 update time in EPC web.
The further question, could you help us to advise the gate driver between LM5177 and EPC2071?

Kind regards,


the LM5177 has a built-in gate driver. Is there a particular reason you are looking for an external one?


Dear Sir,

  1. The EPC9178 can share your vgs of low eGaN waveform in buck mode? I concern the cross-talk effect.
  2. The Vgs of EPC2071 maximum rating is 6V, there need use that LMG1205 to clamping vgs voltage? and further question was that why vgs window of EPC eGaN need have lower negative voltage rating compare other vendor? looks same vgs window △10V, why not shift vgs up to 7~8V to compatible 5V of driver’s voltage?

DC VGS from -4V to 6V

DC VGS from -2V to 8V

  1. The same question post in TI’s e2e forum.
    LM5177: LM5177 with GaN device - Power management forum - Power management - TI E2E support forums

an external gate driver is not needed when using TI LM5117: in EPC9178 we drive our GaN FETs directly from the LO/HO pins. The built-in gate driver laso has a built in 6V clamp, which is compatible with our 6V max rating.
EPC GaN FET are not recommended to be used with negative gate drive:

  • Miller ratio is always <1 so negative drive is not needed to avoid Miller effect
  • negative gate drive will make third quadrant voltage drop higher, which will translate to higher deadtime losses
    All our designs are always done with 0/5V gate drive. To avoid any issues please take a look at our recommended layout guidelines link above.