Dears,
we are developing a 27MHz “class e” amplifier using EPC8010 GAN FET and TI LMG1020 gate driver.
In AN015 appnote, we have seen that the use of “gate return” pin (source Kelvin connection) of the EPC8010 as driver ic ground reference is recommended.
We have a 2-layer PCB board, considering the assembly of the driver and gan on the top layer, i was thinking of making a “driver ground plane” in bottom layer, underneath driver IC and related passive components extended up to fet gate pin, and another ground plane, on the same layer, underneath other components (isolated from the other driver ground plane).
I couldn’t find references in the eval boards docs, do you have any recommendations for best grounding layout policies, for the connection between driver and fet?
Hello Lorenzo,
welcome to the forum and thank you for your interest in our devices.
The EPC8xxx series are the only EPC devices with a dedicated kelvin return pin for gate drive, and they are also optimized for lower capacitances. This translates in larger die size than usual for the same RDSon, which helps power dissipation. They are optimized for few MHz to few 10s of MHz operation.
As explained by AN015, the gate driver can be made “floating” with his ground connected to the gate return terminal of the EPC8010 (pad 2). There might be some ground bounce at the inputs to be managed but AN015 covers it pretty well.
See below pictures. Basically it is very similar to what you are saying.
Since your application is a low side only based converter, with a resonant operation, requirements might be somewhat relaxed, and might be possible also on a 2 layer PCB. While in general, for hard switched applications, we suggest at least 4 layers and using EPC8xxx parts to reach 10+ MHz. Also, separation of the grounds might be avoided and also other EPC devices might be better suited.
Bottom end, to better follow up your case, I suggest you to take this offline and contact me directly: tiziano.morganti@epc-co.com
