|
About the Assembly and Layout category
|
|
0
|
269
|
February 3, 2022
|
|
EPC8010 High speed switching application - Layout recommendation
|
|
1
|
153
|
September 18, 2024
|
|
How much pressure can be applied to the EPC die?
|
|
1
|
707
|
February 27, 2022
|
|
Subnano Pulse Driver Application
|
|
1
|
437
|
January 2, 2024
|
|
Synchronous Bootstrap Circuit
|
|
2
|
627
|
November 9, 2023
|
|
EPC2052 for motor drive
|
|
5
|
635
|
October 17, 2023
|
|
Schottky diode selection
|
|
2
|
590
|
July 5, 2023
|
|
Paste stencil for PQFN devices?
|
|
1
|
360
|
June 22, 2023
|
|
Assembly question
|
|
1
|
447
|
March 16, 2023
|
|
Wafer level chip scale assembly considerations
|
|
1
|
432
|
March 16, 2023
|
|
EPC2212 for LIDAR
|
|
1
|
837
|
December 29, 2022
|
|
Solder Mask Defined pads vs NSMD
|
|
2
|
1349
|
May 10, 2022
|
|
I'm entertaining utilizing the EPC2206 in a new design. Please elaborate/clarify what is meant by "It is recommended to have on-Cu trace PCB vias" on page 6 of the data sheet
|
|
1
|
584
|
February 27, 2022
|
|
Do EPC GaN eFETs pads come pretinted with solder?
|
|
1
|
447
|
February 27, 2022
|
|
Should we be under-filling the GaN FETs for the lab asset?
|
|
1
|
432
|
February 27, 2022
|
|
What is the best way to remove the underfill from the GaNFET with out damaging the FET
|
|
1
|
429
|
February 27, 2022
|
|
What is the best way to remove a GAN FET off a PCB without damaging the FET?
|
|
1
|
440
|
February 27, 2022
|
|
Do we have to use heatsink above the GaN FET?
|
|
1
|
654
|
February 27, 2022
|
|
Are there recommendations for size of via hole in-pad for your GaN devices?
|
|
1
|
418
|
February 27, 2022
|
|
Do you recommend using underfill with your wafer level chipscale packages?
|
|
1
|
448
|
February 27, 2022
|
|
Why is the hard switching gate loop more critical than the GaN acting as a diode and risking induced turn on?
|
|
1
|
542
|
February 27, 2022
|
|
Can you mount the GaN FETs on both sides of the PCB?
|
|
1
|
403
|
February 27, 2022
|
|
I notice you put VIAs under CAP Pads. Is there any solder liability impact?
|
|
1
|
478
|
February 27, 2022
|
|
For 200V GaN, what is the recommended minimum distance between the top and inner layer?
|
|
1
|
442
|
February 27, 2022
|
|
How do we determine the power loop inductance?
|
|
1
|
564
|
February 27, 2022
|
|
How do you measure the VGS and the VDS when you use a very compact layout?
|
|
1
|
429
|
February 27, 2022
|
|
Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA
|
|
1
|
418
|
February 27, 2022
|
|
What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge?
|
|
1
|
403
|
February 27, 2022
|
|
What would be the impact of putting the gate driver in the opposite layer as the FET?
|
|
1
|
357
|
February 27, 2022
|
|
Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance?
|
|
1
|
467
|
February 27, 2022
|