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About the Assembly and Layout category
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0
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280
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February 3, 2022
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EPC8010 High speed switching application - Layout recommendation
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1
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219
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September 18, 2024
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How much pressure can be applied to the EPC die?
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1
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723
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February 27, 2022
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Subnano Pulse Driver Application
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1
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459
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January 2, 2024
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Synchronous Bootstrap Circuit
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2
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656
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November 9, 2023
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EPC2052 for motor drive
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5
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662
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October 17, 2023
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Schottky diode selection
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2
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646
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July 5, 2023
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Paste stencil for PQFN devices?
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1
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370
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June 22, 2023
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Assembly question
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1
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453
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March 16, 2023
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Wafer level chip scale assembly considerations
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1
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463
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March 16, 2023
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EPC2212 for LIDAR
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1
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861
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December 29, 2022
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Solder Mask Defined pads vs NSMD
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2
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1396
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May 10, 2022
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I'm entertaining utilizing the EPC2206 in a new design. Please elaborate/clarify what is meant by "It is recommended to have on-Cu trace PCB vias" on page 6 of the data sheet
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1
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600
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February 27, 2022
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Do EPC GaN eFETs pads come pretinted with solder?
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1
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473
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February 27, 2022
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Should we be under-filling the GaN FETs for the lab asset?
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1
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440
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February 27, 2022
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What is the best way to remove the underfill from the GaNFET with out damaging the FET
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1
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453
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February 27, 2022
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What is the best way to remove a GAN FET off a PCB without damaging the FET?
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1
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467
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February 27, 2022
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Do we have to use heatsink above the GaN FET?
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1
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684
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February 27, 2022
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Are there recommendations for size of via hole in-pad for your GaN devices?
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1
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433
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February 27, 2022
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Do you recommend using underfill with your wafer level chipscale packages?
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1
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472
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February 27, 2022
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Why is the hard switching gate loop more critical than the GaN acting as a diode and risking induced turn on?
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1
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566
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February 27, 2022
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Can you mount the GaN FETs on both sides of the PCB?
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1
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413
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February 27, 2022
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I notice you put VIAs under CAP Pads. Is there any solder liability impact?
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1
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491
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February 27, 2022
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For 200V GaN, what is the recommended minimum distance between the top and inner layer?
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1
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462
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February 27, 2022
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How do we determine the power loop inductance?
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1
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579
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February 27, 2022
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How do you measure the VGS and the VDS when you use a very compact layout?
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1
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439
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February 27, 2022
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Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA
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1
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441
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February 27, 2022
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What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge?
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1
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416
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February 27, 2022
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What would be the impact of putting the gate driver in the opposite layer as the FET?
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1
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378
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February 27, 2022
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Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance?
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1
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479
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February 27, 2022
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