vias
| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| I'm entertaining utilizing the EPC2206 in a new design. Please elaborate/clarify what is meant by "It is recommended to have on-Cu trace PCB vias" on page 6 of the data sheet |
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1 | 53 | February 27, 2022 |
| Are there recommendations for size of via hole in-pad for your GaN devices? |
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1 | 53 | February 27, 2022 |
| I notice you put VIAs under CAP Pads. Is there any solder liability impact? |
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1 | 43 | February 27, 2022 |
| Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA |
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1 | 51 | February 27, 2022 |
| Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance? |
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1 | 53 | February 27, 2022 |
| Can a via be placed directly under a bump? |
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1 | 45 | February 27, 2022 |