Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance?

Designing with GaN FETs and ICs Assembly and Layout
1

Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance? Is it better to have Ground on the top layer without VIAs or can you use the ground layer with VIAs?

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You need to make sure that you have the ground on the first inner layer. View this webinar on best practices for layout and review the “Demonstrations/drawings on Layout Comparisons” slide) If you place the ground anywhere else, it will jeopardize your design.