I’m entertaining utilizing the EPC2206 in a new design. Please elaborate/clarify what is meant by “It is recommended to have on-Cu trace PCB vias” on page 6 of the data sheet. Also, is it acceptable/desirable to have a single long pad that connects adjacent source pads (and adjacent drain pads) underneath the MOSFET?
Layout: yes, it is best (but not required) to have connected adjacent Drain and Source pads. It may be best to show an example, from the evaluation board for EPC2206 (board part number EPC90122). The Gerbers for the board are on the board’s detail page.
Note the gray top layer, how the copper is much larger than the pads. Not only are the adjacent pads connected, but also to a plane on the board. The “pads” are actually solder-mask-defined; openings in the solder mask define the copper pads. This helps in many ways: current carrying, thermal, and assembly (soldering). The Source pins are connected inside the EPC2206, but not an excellent connection, so good external connections (on the board) can help.
“It is recommended to have on-Cu trace PCB vias”: the statement on page 6 of the data sheet. See the EPC2206_gerber-vias.png capture graphic file. The vias (the red stars) are either in the middle of the FET layout shape (Source vias), or near the device edge (Drain vias). It is also possible to do via-in-pad, for best electrical and thermal, but this costs more (vias need to be filled, capped, and plated).
Do you use Altium PCB layout? If so, EPC has an Altium library available. If not, I’d be glad to review schematics and/or layout in the area of the GaN FETs.