How do we determine the power loop inductance? I use Q3D but they do not consider inductance inside the power device, so I think that is not accurate.
This can be done on an existing layout. You can then base your results on other layouts. You can measure the ringing frequency. You need to create a model based on the measures so you can estimate how much you will be getting. It is a mixture of a prediction made on performance and experience based on experiment and assessment. If you follow our optimal vertical layout, you should end up in the range of 0.4-0.5 nH. For more information, refer to the webinar High-perormance layout techniques to maximize GaN device performance