I am loking into designing a board with the EPC2035 GaN transistor, and for the design it has to sustain 60V Vds. I am looking at the layout of the system, specially to the clearance, due to the standards for high voltage designs.
According to the IPC2221B standard, for a 60V delta between 2 connectors/terminations in an external component (category A6 in the standard), at least 0.5mm of clearance are required. However, the EPC2035 has 0.242mm clearance between 2 pins that can have up to 60V delta. How can I satisfy the standard with a design with this GaN? How important is it?
Hello, and thank you for your interest in our devices.
The parts with narrower pitch have been developed to minimize the parasitics, and there are applications were you can use lower clearance than that recommended by IPC-2221, table 6-1, category A6 . In example not only by using conformal coating (category A7), but also final use in clean environment (sealed solutions or filtered air cooling like in data centers). There are techniques to mitigate the risks, which include rinsing the board after soldering, and assuring a complete curing of the flux by careful choice of reflow profile. You can refer to our AN009 for details:
Depending on your requirements, if IPC-2221 is a must have, you might want to look at other parts: I can recommend EPC2054 (0.4mm clearance, still not meeting IPC-2221, but closer).