For the rectifier FET having higher gate loop inductance makes it difficult to keep the FET off in case of SW transition, like when the SW flies up in the case of a buck. How is this solved if a gate loop is optimized for only the controlled FET?

Designing with GaN FETs and ICs
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1

For the rectifier FET having higher gate loop inductance makes it difficult to keep the FET off in case of SW transition, like when the SW flies up in the case of a buck. How is this solved if a gate loop is optimized for only the controlled FET?

2

What is important when dealing with GaN FET is always using gate drivers which are made for GaN FET. A typical gate driver for a GaN FET has two outputs. One output is to switch on, the other to switch off - Details of this can be found in the webinar High-performance layout techniques to maximize GaN device performance.