Could you please clarify the switching times characteristics of GaN FETs?
This really depends on the gate drive current. Our transistor is voltage controlled, so the switching time is derived from the time it takes to charge the parasitic capacitances (Cgs, Cgd).
It is similar to Si MOSFETs, except our capacitances and charges are one order of magnitude smaller.
In our specs, current rise time is the time it takes to charge QGS2 and Voltage fall time is the time it takes to charge QGD. Layout parasitics can reduce the switching speed, especially the common source inductance, which at the end removes “drive” from the gate.
For additional reference please view https://epc-co.com/epc/Portals/0/epc/documents/presentations/EPC_Paralleling_High_Speed_GAN_Reusch.pdf
Can you clarify the characteristics of the anti-parallel intrinsic diode? Silicon MOSFETS normally have the same current rating as the Drain Source forward current, how about GaN FETs?