What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge?
If you are paralleling the half-bridges, you are not paralleling the FETs. You must make sure you are always paralleling your half bridges and you are keeping your layout, and not simply paralleling the devices and not following the main rules. What is important is that each device must have its own gate resistors coming and going to the gate drive. It is important to equalize the path from gate driver to each device so that they switch on at the same time. The more parts you put in parallel, the more difficult it becomes. We have seen a successful design that has 12 half bridges in parallel. You need to decide where to place your gate driver (it can be on the bottom) and how the gate signal is going to go to all the half bridges in an equalized way.