|
What is the best place to find general information on applying EPC’s enhancement mode GaN power devices?
|
|
1
|
546
|
February 28, 2022
|
|
Is a 2 kilowatt isolated DC-DC @ 48 volts unregulated full bridge configuration doable with GaN?
|
|
1
|
580
|
February 28, 2022
|
|
Do you have an example for a 3-phase inverter?
|
|
1
|
560
|
February 28, 2022
|
|
I want to design a PCB which can trigger high power laser with about 30MHz (if possible)
|
|
1
|
604
|
February 28, 2022
|
|
I plan to use four EPC2012C to make a full-bridge inverter for driving a wireless power transmitting coil. The input DC voltage is up to 120 V. Can you recommend a GaN-friendly half bridge driver for these conditions
|
|
1
|
549
|
February 28, 2022
|
|
Using the EPC21601, is it possible to drive the gates of a BLF189XRA (1500 Watt Power LDMOS) in a push pull manner
|
|
1
|
603
|
February 28, 2022
|
|
Do the logic signals have to be isolated from the IC on the EPC2152 ePower™ Stage's HS and LS pins?
|
|
1
|
508
|
February 28, 2022
|
|
What is the best way to connect the SUBSTRATE pin on the EPC2010C or should we connect it at all?
|
|
1
|
706
|
February 28, 2022
|
|
Is it possible to use two 100 V GaN FETs in series for a 150 V laser driver application
|
|
1
|
538
|
February 28, 2022
|
|
How do I predict failure rates for the EPC eGaN FETs?
|
|
1
|
503
|
February 28, 2022
|
|
What is the expected HBM (Human Body Model) ESD rating of the parts? Is there special handling required?
|
|
1
|
537
|
February 28, 2022
|
|
Is there reliability data (MTBF, FITS) available for the EPC eGaN transistors?
|
|
1
|
587
|
February 28, 2022
|
|
I'm entertaining utilizing the EPC2206 in a new design. Please elaborate/clarify what is meant by "It is recommended to have on-Cu trace PCB vias" on page 6 of the data sheet
|
|
1
|
585
|
February 27, 2022
|
|
Do EPC GaN eFETs pads come pretinted with solder?
|
|
1
|
448
|
February 27, 2022
|
|
Should we be under-filling the GaN FETs for the lab asset?
|
|
1
|
433
|
February 27, 2022
|
|
What is the best way to remove the underfill from the GaNFET with out damaging the FET
|
|
1
|
431
|
February 27, 2022
|
|
What is the best way to remove a GAN FET off a PCB without damaging the FET?
|
|
1
|
441
|
February 27, 2022
|
|
Do we have to use heatsink above the GaN FET?
|
|
1
|
660
|
February 27, 2022
|
|
Are there recommendations for size of via hole in-pad for your GaN devices?
|
|
1
|
420
|
February 27, 2022
|
|
Do you recommend using underfill with your wafer level chipscale packages?
|
|
1
|
450
|
February 27, 2022
|
|
Why is the hard switching gate loop more critical than the GaN acting as a diode and risking induced turn on?
|
|
1
|
547
|
February 27, 2022
|
|
Can you mount the GaN FETs on both sides of the PCB?
|
|
1
|
405
|
February 27, 2022
|
|
I notice you put VIAs under CAP Pads. Is there any solder liability impact?
|
|
1
|
480
|
February 27, 2022
|
|
For 200V GaN, what is the recommended minimum distance between the top and inner layer?
|
|
1
|
444
|
February 27, 2022
|
|
How do we determine the power loop inductance?
|
|
1
|
567
|
February 27, 2022
|
|
How do you measure the VGS and the VDS when you use a very compact layout?
|
|
1
|
430
|
February 27, 2022
|
|
Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA
|
|
1
|
420
|
February 27, 2022
|
|
What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge?
|
|
1
|
405
|
February 27, 2022
|
|
What would be the impact of putting the gate driver in the opposite layer as the FET?
|
|
1
|
358
|
February 27, 2022
|
|
Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance?
|
|
1
|
468
|
February 27, 2022
|