GaN Talk Support Forum EPC

Topic	Replies	Views	Activity
Do EPC GaN eFETs pads come pretinted with solder? Assembly and Layout solder , flux	1	557	February 27, 2022
Should we be under-filling the GaN FETs for the lab asset? Assembly and Layout temperature	1	541	February 27, 2022
What is the best way to remove the underfill from the GaNFET with out damaging the FET Assembly and Layout underfill	1	531	February 27, 2022
What is the best way to remove a GAN FET off a PCB without damaging the FET? Assembly and Layout pcb	1	574	February 27, 2022
Do we have to use heatsink above the GaN FET? Assembly and Layout heatsink	1	767	February 27, 2022
Are there recommendations for size of via hole in-pad for your GaN devices? Assembly and Layout vias	1	497	February 27, 2022
Do you recommend using underfill with your wafer level chipscale packages? Assembly and Layout	1	535	February 27, 2022
Why is the hard switching gate loop more critical than the GaN acting as a diode and risking induced turn on? Assembly and Layout diodes	1	615	February 27, 2022
Can you mount the GaN FETs on both sides of the PCB? Assembly and Layout pcb	1	505	February 27, 2022
I notice you put VIAs under CAP Pads. Is there any solder liability impact? Assembly and Layout solder , vias	1	581	February 27, 2022
For 200V GaN, what is the recommended minimum distance between the top and inner layer? Assembly and Layout	1	513	February 27, 2022
How do we determine the power loop inductance? Assembly and Layout inductance	1	649	February 27, 2022
How do you measure the VGS and the VDS when you use a very compact layout? Assembly and Layout layout	1	578	February 27, 2022
Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA Assembly and Layout vias	1	526	February 27, 2022
What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge? Assembly and Layout gate-drive	1	525	February 27, 2022
What would be the impact of putting the gate driver in the opposite layer as the FET? Assembly and Layout gate-drive	1	449	February 27, 2022
Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance? Assembly and Layout vias	1	525	February 27, 2022
What is the copper layer thickness for power & ground layer? What is the formula for current calculations? Assembly and Layout	1	514	February 27, 2022
What is the best method to remove heat from a 2 kilowatt isolated DC-DC @ 48 V unregulated full bridge? DC-DC Conversion temperature , thermal , data-center , dc-dc , consumer	1	645	February 27, 2022
What are common issues EPC has encountered in PCB design and assembly? Assembly and Layout design , pcb	1	441	February 27, 2022
Do the EPC eGaN parts require under-fill during manufacturing? Assembly and Layout manufacturing	1	703	February 27, 2022
Can a water rinseable solder flux be used in assembling lead free (PbF) eGaN FETs? Assembly and Layout solder	1	519	February 27, 2022
What does EPC recommend for solder flux being used in assembling lead free (PbF) eGaN FETs? Assembly and Layout solder	1	544	February 27, 2022
What tacky flux can be used for assembling the EPC lead free (PbF) die? Assembly and Layout	1	334	February 27, 2022
What considerations need to be made in regard to stencil design? Assembly and Layout design	1	566	February 27, 2022
What lead free (PbF) solder pastes has EPC used? Assembly and Layout solder	1	465	February 27, 2022
Can a via be placed directly under a bump? Assembly and Layout design , vias	1	729	February 27, 2022
What is the recommended reflow for EPC die? Assembly and Layout	1	525	February 27, 2022
What is the composition of the lead free (PbF) solder bump and underbump (UBM) metals for EPC die? Assembly and Layout solder	1	425	February 27, 2022
How do I assemble EPC’s enhancement mode GaN devices and do these parts require any special steps during the manufacturing process? Assembly and Layout	1	474	February 27, 2022