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The high frequency capability of the devices could be an issue with the layout of my circuit board. What must I be mindful of when laying out my circuit?
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1
|
653
|
February 28, 2022
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What is the best place to find general information on applying EPC’s enhancement mode GaN power devices?
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1
|
732
|
February 28, 2022
|
|
Is a 2 kilowatt isolated DC-DC @ 48 volts unregulated full bridge configuration doable with GaN?
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1
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741
|
February 28, 2022
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Do you have an example for a 3-phase inverter?
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1
|
752
|
February 28, 2022
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I want to design a PCB which can trigger high power laser with about 30MHz (if possible)
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1
|
766
|
February 28, 2022
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|
I plan to use four EPC2012C to make a full-bridge inverter for driving a wireless power transmitting coil. The input DC voltage is up to 120 V. Can you recommend a GaN-friendly half bridge driver for these conditions
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1
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730
|
February 28, 2022
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Using the EPC21601, is it possible to drive the gates of a BLF189XRA (1500 Watt Power LDMOS) in a push pull manner
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1
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827
|
February 28, 2022
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Do the logic signals have to be isolated from the IC on the EPC2152 ePower™ Stage's HS and LS pins?
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1
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645
|
February 28, 2022
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What is the best way to connect the SUBSTRATE pin on the EPC2010C or should we connect it at all?
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1
|
1021
|
February 28, 2022
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Is it possible to use two 100 V GaN FETs in series for a 150 V laser driver application
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1
|
809
|
February 28, 2022
|
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How do I predict failure rates for the EPC eGaN FETs?
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1
|
665
|
February 28, 2022
|
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What is the expected HBM (Human Body Model) ESD rating of the parts? Is there special handling required?
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1
|
767
|
February 28, 2022
|
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Is there reliability data (MTBF, FITS) available for the EPC eGaN transistors?
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1
|
775
|
February 28, 2022
|
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I'm entertaining utilizing the EPC2206 in a new design. Please elaborate/clarify what is meant by "It is recommended to have on-Cu trace PCB vias" on page 6 of the data sheet
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1
|
792
|
February 27, 2022
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Do EPC GaN eFETs pads come pretinted with solder?
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1
|
643
|
February 27, 2022
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Should we be under-filling the GaN FETs for the lab asset?
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1
|
607
|
February 27, 2022
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What is the best way to remove the underfill from the GaNFET with out damaging the FET
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1
|
625
|
February 27, 2022
|
|
What is the best way to remove a GAN FET off a PCB without damaging the FET?
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1
|
690
|
February 27, 2022
|
|
Do we have to use heatsink above the GaN FET?
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1
|
884
|
February 27, 2022
|
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Are there recommendations for size of via hole in-pad for your GaN devices?
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1
|
579
|
February 27, 2022
|
|
Do you recommend using underfill with your wafer level chipscale packages?
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1
|
604
|
February 27, 2022
|
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Why is the hard switching gate loop more critical than the GaN acting as a diode and risking induced turn on?
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1
|
692
|
February 27, 2022
|
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Can you mount the GaN FETs on both sides of the PCB?
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1
|
572
|
February 27, 2022
|
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I notice you put VIAs under CAP Pads. Is there any solder liability impact?
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1
|
654
|
February 27, 2022
|
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For 200V GaN, what is the recommended minimum distance between the top and inner layer?
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|
1
|
568
|
February 27, 2022
|
|
How do we determine the power loop inductance?
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|
1
|
735
|
February 27, 2022
|
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How do you measure the VGS and the VDS when you use a very compact layout?
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1
|
685
|
February 27, 2022
|
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Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA
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1
|
595
|
February 27, 2022
|
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What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge?
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|
1
|
600
|
February 27, 2022
|
|
What would be the impact of putting the gate driver in the opposite layer as the FET?
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|
1
|
529
|
February 27, 2022
|