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Is it possible to use two 100 V GaN FETs in series for a 150 V laser driver application
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1
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729
|
February 28, 2022
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How do I predict failure rates for the EPC eGaN FETs?
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1
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628
|
February 28, 2022
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What is the expected HBM (Human Body Model) ESD rating of the parts? Is there special handling required?
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1
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721
|
February 28, 2022
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Is there reliability data (MTBF, FITS) available for the EPC eGaN transistors?
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1
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733
|
February 28, 2022
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I'm entertaining utilizing the EPC2206 in a new design. Please elaborate/clarify what is meant by "It is recommended to have on-Cu trace PCB vias" on page 6 of the data sheet
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1
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731
|
February 27, 2022
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Do EPC GaN eFETs pads come pretinted with solder?
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1
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590
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February 27, 2022
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Should we be under-filling the GaN FETs for the lab asset?
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1
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566
|
February 27, 2022
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What is the best way to remove the underfill from the GaNFET with out damaging the FET
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1
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572
|
February 27, 2022
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What is the best way to remove a GAN FET off a PCB without damaging the FET?
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1
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625
|
February 27, 2022
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Do we have to use heatsink above the GaN FET?
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1
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817
|
February 27, 2022
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Are there recommendations for size of via hole in-pad for your GaN devices?
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1
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528
|
February 27, 2022
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Do you recommend using underfill with your wafer level chipscale packages?
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1
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568
|
February 27, 2022
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Why is the hard switching gate loop more critical than the GaN acting as a diode and risking induced turn on?
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1
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645
|
February 27, 2022
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Can you mount the GaN FETs on both sides of the PCB?
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1
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535
|
February 27, 2022
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I notice you put VIAs under CAP Pads. Is there any solder liability impact?
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1
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615
|
February 27, 2022
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For 200V GaN, what is the recommended minimum distance between the top and inner layer?
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1
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540
|
February 27, 2022
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How do we determine the power loop inductance?
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1
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691
|
February 27, 2022
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How do you measure the VGS and the VDS when you use a very compact layout?
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1
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633
|
February 27, 2022
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Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA
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1
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551
|
February 27, 2022
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What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge?
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1
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559
|
February 27, 2022
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What would be the impact of putting the gate driver in the opposite layer as the FET?
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1
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494
|
February 27, 2022
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Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance?
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1
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552
|
February 27, 2022
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What is the copper layer thickness for power & ground layer? What is the formula for current calculations?
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1
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544
|
February 27, 2022
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What is the best method to remove heat from a 2 kilowatt isolated DC-DC @ 48 V unregulated full bridge?
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1
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683
|
February 27, 2022
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What are common issues EPC has encountered in PCB design and assembly?
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1
|
471
|
February 27, 2022
|
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Do the EPC eGaN parts require under-fill during manufacturing?
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1
|
739
|
February 27, 2022
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Can a water rinseable solder flux be used in assembling lead free (PbF) eGaN FETs?
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1
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542
|
February 27, 2022
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What does EPC recommend for solder flux being used in assembling lead free (PbF) eGaN FETs?
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1
|
574
|
February 27, 2022
|
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What tacky flux can be used for assembling the EPC lead free (PbF) die?
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1
|
358
|
February 27, 2022
|
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What considerations need to be made in regard to stencil design?
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1
|
611
|
February 27, 2022
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