Designing with GaN FETs and ICs

Topic	Replies	Views	Activity
I'm planning to use the an EPC GaN FET to sink around 30A for a period of around 3 microseconds Designing with GaN FETs and ICs pulse , aerospace-defense , medtech , data-center , current	1	702	March 1, 2022
How do you recommend heatsinking EPC's wafer level chip scale packages? Designing with GaN FETs and ICs heatsink , automotive , dc-dc , industrial , thermal	1	749	March 1, 2022
Is it advisable to put CM chokes on PI type filters at the input of the gate driver? Designing with GaN FETs and ICs gate-drive , design , dc-dc , communications , industrial	1	580	February 28, 2022
Are there any app notes that show loss factor effects based on a switching frequency of 500 kilohertz instead of 1 megahertz? Designing with GaN FETs and ICs application-notes , dc-dc , industrial , consumer , data-center	1	686	February 28, 2022
For the rectifier FET having higher gate loop inductance makes it difficult to keep the FET off in case of SW transition, like when the SW flies up in the case of a buck. How is this solved if a gate loop is optimized for only the controlled FET? Designing with GaN FETs and ICs buck , dc-dc	1	592	February 28, 2022
I am looking for 60V/100A GaN mosfet, do you have any similar product available in the market? Designing with GaN FETs and ICs	1	572	February 28, 2022
Is it possible to provide step/CAD files of the chip? Designing with GaN FETs and ICs step , cad	1	553	February 28, 2022
What method do you recommend to measure the case temperature of EPC devices? Designing with GaN FETs and ICs temperature	1	785	February 28, 2022
Do you have models for your products? Designing with GaN FETs and ICs	1	465	February 28, 2022
Do you see a problem if the difference between VDD, VBoot and VIN is Zero? Designing with GaN FETs and ICs	1	1005	February 28, 2022
We wish to employ liquid cooling which is why the GaN FETs will be mounted on an IMS board Designing with GaN FETs and ICs	1	591	February 28, 2022
How do I choose the best driver for my application? Designing with GaN FETs and ICs driver	1	623	February 28, 2022
How do you determine the value of the optimal dead time to have the best efficiency? Designing with GaN FETs and ICs dead-time	1	734	February 28, 2022
In the LTSpice models, are the parasitic capacitances integrated directly into the model of EPC GaN FETs or do they have to be added? Designing with GaN FETs and ICs ltspice	1	771	February 28, 2022
I'm entertaining utilizing the EPC2206 in a new design. Please elaborate/clarify what is meant by "It is recommended to have on-Cu trace PCB vias" on page 6 of the data sheet Assembly and Layout vias , pcb , design	1	876	February 27, 2022
Do EPC GaN eFETs pads come pretinted with solder? Assembly and Layout solder , flux	1	733	February 27, 2022
Should we be under-filling the GaN FETs for the lab asset? Assembly and Layout temperature	1	669	February 27, 2022
What is the best way to remove the underfill from the GaNFET with out damaging the FET Assembly and Layout underfill	1	701	February 27, 2022
What is the best way to remove a GAN FET off a PCB without damaging the FET? Assembly and Layout pcb	1	879	February 27, 2022
Do we have to use heatsink above the GaN FET? Assembly and Layout heatsink	1	988	February 27, 2022
Are there recommendations for size of via hole in-pad for your GaN devices? Assembly and Layout vias	1	696	February 27, 2022
Do you recommend using underfill with your wafer level chipscale packages? Assembly and Layout	1	744	February 27, 2022
Why is the hard switching gate loop more critical than the GaN acting as a diode and risking induced turn on? Assembly and Layout diodes	1	751	February 27, 2022
Can you mount the GaN FETs on both sides of the PCB? Assembly and Layout pcb	1	650	February 27, 2022
I notice you put VIAs under CAP Pads. Is there any solder liability impact? Assembly and Layout solder , vias	1	728	February 27, 2022
For 200V GaN, what is the recommended minimum distance between the top and inner layer? Assembly and Layout	1	631	February 27, 2022
How do we determine the power loop inductance? Assembly and Layout inductance	1	813	February 27, 2022
How do you measure the VGS and the VDS when you use a very compact layout? Assembly and Layout layout	1	796	February 27, 2022
Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA Assembly and Layout vias	1	675	February 27, 2022
What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge? Assembly and Layout gate-drive	1	648	February 27, 2022