Designing with GaN FETs and ICs

Topic	Replies	Views	Activity
What is the best way to remove a GAN FET off a PCB without damaging the FET? Assembly and Layout pcb	1	468	February 27, 2022
Do we have to use heatsink above the GaN FET? Assembly and Layout heatsink	1	687	February 27, 2022
Are there recommendations for size of via hole in-pad for your GaN devices? Assembly and Layout vias	1	441	February 27, 2022
Do you recommend using underfill with your wafer level chipscale packages? Assembly and Layout	1	476	February 27, 2022
Why is the hard switching gate loop more critical than the GaN acting as a diode and risking induced turn on? Assembly and Layout diodes	1	568	February 27, 2022
Can you mount the GaN FETs on both sides of the PCB? Assembly and Layout pcb	1	417	February 27, 2022
I notice you put VIAs under CAP Pads. Is there any solder liability impact? Assembly and Layout solder , vias	1	500	February 27, 2022
For 200V GaN, what is the recommended minimum distance between the top and inner layer? Assembly and Layout	1	465	February 27, 2022
How do we determine the power loop inductance? Assembly and Layout inductance	1	582	February 27, 2022
How do you measure the VGS and the VDS when you use a very compact layout? Assembly and Layout layout	1	444	February 27, 2022
Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA Assembly and Layout vias	1	447	February 27, 2022
What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge? Assembly and Layout gate-drive	1	423	February 27, 2022
What would be the impact of putting the gate driver in the opposite layer as the FET? Assembly and Layout gate-drive	1	382	February 27, 2022
Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance? Assembly and Layout vias	1	482	February 27, 2022
What is the copper layer thickness for power & ground layer? What is the formula for current calculations? Assembly and Layout	1	462	February 27, 2022
What are common issues EPC has encountered in PCB design and assembly? Assembly and Layout design , pcb	1	389	February 27, 2022
Do the EPC eGaN parts require under-fill during manufacturing? Assembly and Layout manufacturing	1	570	February 27, 2022
Can a water rinseable solder flux be used in assembling lead free (PbF) eGaN FETs? Assembly and Layout solder	1	441	February 27, 2022
What does EPC recommend for solder flux being used in assembling lead free (PbF) eGaN FETs? Assembly and Layout solder	1	435	February 27, 2022
What tacky flux can be used for assembling the EPC lead free (PbF) die? Assembly and Layout	1	287	February 27, 2022
What considerations need to be made in regard to stencil design? Assembly and Layout design	1	460	February 27, 2022
What lead free (PbF) solder pastes has EPC used? Assembly and Layout solder	1	339	February 27, 2022
Can a via be placed directly under a bump? Assembly and Layout design , vias	1	596	February 27, 2022
What is the recommended reflow for EPC die? Assembly and Layout	1	424	February 27, 2022
What is the composition of the lead free (PbF) solder bump and underbump (UBM) metals for EPC die? Assembly and Layout solder	1	365	February 27, 2022
How do I assemble EPC’s enhancement mode GaN devices and do these parts require any special steps during the manufacturing process? Assembly and Layout	1	378	February 27, 2022