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Are there any app notes that show loss factor effects based on a switching frequency of 500 kilohertz instead of 1 megahertz?
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1
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678
|
February 28, 2022
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For the rectifier FET having higher gate loop inductance makes it difficult to keep the FET off in case of SW transition, like when the SW flies up in the case of a buck. How is this solved if a gate loop is optimized for only the controlled FET?
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1
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572
|
February 28, 2022
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I am looking for 60V/100A GaN mosfet, do you have any similar product available in the market?
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1
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559
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February 28, 2022
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Is it possible to provide step/CAD files of the chip?
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1
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541
|
February 28, 2022
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What method do you recommend to measure the case temperature of EPC devices?
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1
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770
|
February 28, 2022
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Do you have models for your products?
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1
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453
|
February 28, 2022
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Do you see a problem if the difference between VDD, VBoot and VIN is Zero?
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1
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989
|
February 28, 2022
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We wish to employ liquid cooling which is why the GaN FETs will be mounted on an IMS board
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1
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575
|
February 28, 2022
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How do I choose the best driver for my application?
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1
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619
|
February 28, 2022
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How do you determine the value of the optimal dead time to have the best efficiency?
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1
|
713
|
February 28, 2022
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In the LTSpice models, are the parasitic capacitances integrated directly into the model of EPC GaN FETs or do they have to be added?
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1
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763
|
February 28, 2022
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I'm entertaining utilizing the EPC2206 in a new design. Please elaborate/clarify what is meant by "It is recommended to have on-Cu trace PCB vias" on page 6 of the data sheet
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1
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864
|
February 27, 2022
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Do EPC GaN eFETs pads come pretinted with solder?
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1
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717
|
February 27, 2022
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Should we be under-filling the GaN FETs for the lab asset?
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1
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660
|
February 27, 2022
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What is the best way to remove the underfill from the GaNFET with out damaging the FET
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1
|
692
|
February 27, 2022
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What is the best way to remove a GAN FET off a PCB without damaging the FET?
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1
|
859
|
February 27, 2022
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Do we have to use heatsink above the GaN FET?
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1
|
978
|
February 27, 2022
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Are there recommendations for size of via hole in-pad for your GaN devices?
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1
|
685
|
February 27, 2022
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Do you recommend using underfill with your wafer level chipscale packages?
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1
|
719
|
February 27, 2022
|
|
Why is the hard switching gate loop more critical than the GaN acting as a diode and risking induced turn on?
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1
|
746
|
February 27, 2022
|
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Can you mount the GaN FETs on both sides of the PCB?
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1
|
636
|
February 27, 2022
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I notice you put VIAs under CAP Pads. Is there any solder liability impact?
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1
|
715
|
February 27, 2022
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For 200V GaN, what is the recommended minimum distance between the top and inner layer?
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1
|
621
|
February 27, 2022
|
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How do we determine the power loop inductance?
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1
|
803
|
February 27, 2022
|
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How do you measure the VGS and the VDS when you use a very compact layout?
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1
|
782
|
February 27, 2022
|
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Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA
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1
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662
|
February 27, 2022
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What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge?
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1
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643
|
February 27, 2022
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What would be the impact of putting the gate driver in the opposite layer as the FET?
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1
|
579
|
February 27, 2022
|
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Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance?
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1
|
639
|
February 27, 2022
|
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What is the copper layer thickness for power & ground layer? What is the formula for current calculations?
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1
|
632
|
February 27, 2022
|