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How do we determine the power loop inductance?
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1
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61
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February 27, 2022
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How do you measure the VGS and the VDS when you use a very compact layout?
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1
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47
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February 27, 2022
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Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA
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1
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51
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February 27, 2022
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What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge?
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1
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44
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February 27, 2022
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What would be the impact of putting the gate driver in the opposite layer as the FET?
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1
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53
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February 27, 2022
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Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance?
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1
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53
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February 27, 2022
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What is the copper layer thickness for power & ground layer? What is the formula for current calculations?
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1
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37
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February 27, 2022
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What are common issues EPC has encountered in PCB design and assembly?
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1
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42
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February 27, 2022
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How much pressure can be applied to the EPC die?
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1
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44
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February 27, 2022
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Do the EPC eGaN parts require under-fill during manufacturing?
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1
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40
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February 27, 2022
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Can a water rinseable solder flux be used in assembling lead free (PbF) eGaN FETs?
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1
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55
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February 27, 2022
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What does EPC recommend for solder flux being used in assembling lead free (PbF) eGaN FETs?
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1
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34
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February 27, 2022
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What tacky flux can be used for assembling the EPC lead free (PbF) die?
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1
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46
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February 27, 2022
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What considerations need to be made in regard to stencil design?
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1
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46
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February 27, 2022
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What lead free (PbF) solder pastes has EPC used?
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1
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40
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February 27, 2022
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Can a via be placed directly under a bump?
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1
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45
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February 27, 2022
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What is the recommended reflow for EPC die?
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1
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38
|
February 27, 2022
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What is the composition of the lead free (PbF) solder bump and underbump (UBM) metals for EPC die?
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1
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48
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February 27, 2022
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How do I assemble EPC’s enhancement mode GaN devices and do these parts require any special steps during the manufacturing process?
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1
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20
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February 27, 2022
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