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Should we be under-filling the GaN FETs for the lab asset?
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1
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68
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February 27, 2022
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What is the best way to remove the underfill from the GaNFET with out damaging the FET
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1
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73
|
February 27, 2022
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What is the best way to remove a GAN FET off a PCB without damaging the FET?
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1
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90
|
February 27, 2022
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Do we have to use heatsink above the GaN FET?
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1
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127
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February 27, 2022
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Are there recommendations for size of via hole in-pad for your GaN devices?
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1
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86
|
February 27, 2022
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Do you recommend using underfill with your wafer level chipscale packages?
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1
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84
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February 27, 2022
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Why is the hard switching gate loop more critical than the GaN acting as a diode and risking induced turn on?
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1
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84
|
February 27, 2022
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Can you mount the GaN FETs on both sides of the PCB?
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1
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74
|
February 27, 2022
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I notice you put VIAs under CAP Pads. Is there any solder liability impact?
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1
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82
|
February 27, 2022
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For 200V GaN, what is the recommended minimum distance between the top and inner layer?
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1
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89
|
February 27, 2022
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How do we determine the power loop inductance?
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1
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108
|
February 27, 2022
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How do you measure the VGS and the VDS when you use a very compact layout?
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1
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77
|
February 27, 2022
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Why is it better to have the gate drive return to the inner layer with VIA than going to source on the lower FET directly with no VIA
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1
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83
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February 27, 2022
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What would you advise for high current designs, paralleling multiple FETs closer to each other or paralleling outputs of multiple separate half bridges with optimal layout per half bridge?
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1
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77
|
February 27, 2022
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What would be the impact of putting the gate driver in the opposite layer as the FET?
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1
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89
|
February 27, 2022
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Is C bypass Hi FET @ low FET ground the best way to optimize loop inductance?
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1
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80
|
February 27, 2022
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What is the copper layer thickness for power & ground layer? What is the formula for current calculations?
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1
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63
|
February 27, 2022
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What are common issues EPC has encountered in PCB design and assembly?
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1
|
80
|
February 27, 2022
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How much pressure can be applied to the EPC die?
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1
|
68
|
February 27, 2022
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Do the EPC eGaN parts require under-fill during manufacturing?
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1
|
72
|
February 27, 2022
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Can a water rinseable solder flux be used in assembling lead free (PbF) eGaN FETs?
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1
|
90
|
February 27, 2022
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What does EPC recommend for solder flux being used in assembling lead free (PbF) eGaN FETs?
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1
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75
|
February 27, 2022
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What tacky flux can be used for assembling the EPC lead free (PbF) die?
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1
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72
|
February 27, 2022
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What considerations need to be made in regard to stencil design?
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1
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77
|
February 27, 2022
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What lead free (PbF) solder pastes has EPC used?
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1
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71
|
February 27, 2022
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Can a via be placed directly under a bump?
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1
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76
|
February 27, 2022
|
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What is the recommended reflow for EPC die?
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1
|
77
|
February 27, 2022
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What is the composition of the lead free (PbF) solder bump and underbump (UBM) metals for EPC die?
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1
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76
|
February 27, 2022
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How do I assemble EPC’s enhancement mode GaN devices and do these parts require any special steps during the manufacturing process?
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1
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43
|
February 27, 2022
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